Layout context-based cell timing characterization

ABSTRACT

A method performed by at least one processor includes the following steps. A layout of an integrated circuit (IC) is accessed, wherein the layout has at least one cell. A context group for the cell is determined based on a layout context of the cell, wherein the context group is associated with a timing table. A timing analysis is performed on the layout to determine whether the layout complies with a timing constraint rule according to the timing table. A system including one or more processors including instructions for implementing the method and a non-transitory computer readable storage medium including instructions for implementing the method are also provided.

BACKGROUND

In advanced semiconductor technologies, continuing reduction in devicesize and increasingly complex circuit arrangements have made the designand fabrication of integrated circuits (ICs) more challenging andcostly. In the flow of modern circuit design methodology, the designedcircuit must be tested to confirm it meets the design specification andmanufacturing criteria before it is delivered for mass production. Suchconfirmation of millions of transistor devices is difficult, if notimpossible, to accomplish manually in an efficient and precise manner.Electronic Design Automation (EDA) tools have been introduced to aid indesigning and troubleshooting the electronic circuits to increase designefficiency and reduce design errors. Moreover, various design librariesare provided to reduce the effort of building commonly used functionalblocks in the circuit. However, although the EDA tools have progressedsignificantly, they are still not satisfactory in many aspects. Forexample, the libraries usually provide parameters with larger marginsthan necessary in order to accommodate as many interconnectionconditions as possible and ensure that the manufactured circuitfabricated based on the libraries functions correctly. As a result, thecircuit may be fabricated with suboptimal efficiency in power, area orperformance. Therefore, there is a need to improve the EDA-aided designflow to reduce unnecessary design margins while maintaining the circuitperformance.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It shouldbe noted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 is a schematic diagram illustrating a design flow of anintegrated circuit (IC), in accordance with some embodiments of thepresent disclosure.

FIG. 2 is a schematic diagram of a context grouping process, inaccordance with some embodiments of the present disclosure.

FIG. 3A is an exemplary layout, in accordance with some embodiments ofthe present disclosure.

FIGS. 3B to 3E are various exemplary layout contexts of a cell, inaccordance with some embodiments of the present disclosure.

FIG. 3F is a schematic diagram of a training model, in accordance withsome embodiments of the present disclosure.

FIG. 4A is a schematic diagram of a result of a context grouping, inaccordance with some embodiments of the present disclosure.

FIG. 4B is a schematic diagram of a chart displaying timing delaydistributions of different context groups, in accordance with someembodiments of the present disclosure.

FIG. 5A is a schematic diagram showing a context-aware cell recognitionalgorithm, in accordance with some embodiments of the presentdisclosure.

FIG. 5B is a schematic diagram showing a timing table of a contextgroup, in accordance with some embodiments of the present disclosure.

FIG. 6 is a flowchart of a method of a context-aware cell recognitionalgorithm, in accordance with some embodiments of the presentdisclosure.

FIG. 7 is a schematic diagram of a system implementing layout design, inaccordance with some embodiments.

DETAILED DESCRIPTION

In the following detailed description, numerous specific details are setforth in order to provide a thorough understanding of the presentdisclosure. However, it will be understood by those skilled in the artthat the present disclosure may be practiced without these specificdetails. In other instances, well-known methods, procedures, componentsand circuits are not described in detail so as not to obscure thepresent disclosure.

Further, the present disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

Notwithstanding that the numerical ranges and parameters setting forththe broad scope of the disclosure are approximations, the numericalvalues set forth in the specific examples are reported as precisely aspossible. Any numerical value, however, inherently contains certainerrors necessarily resulting from the deviation normally found in therespective testing measurements. Also, as used herein, the terms“about,” “substantial” or “substantially” generally mean within 10%, 5%,1% or 0.5% of a given value or range. Alternatively, the terms “about,”“substantial” or “substantially” mean within an acceptable standarderror of the mean when considered by one of ordinary skill in the art.Other than in the operating/working examples, or unless otherwiseexpressly specified, all of the numerical ranges, amounts, values andpercentages such as those for quantities of materials, durations oftimes, temperatures, operating conditions, ratios of amounts, and thelikes thereof disclosed herein should be understood as modified in allinstances by the terms “about,” “substantial” or “substantially.”Accordingly, unless indicated to the contrary, the numerical parametersset forth in the present disclosure and attached claims areapproximations that can vary as desired. At the very least, eachnumerical parameter should at least be construed in light of the numberof reported significant digits and by applying ordinary roundingtechniques. Ranges can be expressed herein as from one endpoint toanother endpoint or between two endpoints. All ranges disclosed hereinare inclusive of the endpoints, unless specified otherwise.

Throughout the present disclosure, the term “active region” refers to aplanar area of a surface of a semiconductor device in (or over) whichthe major components of a semiconductor transistor are formed. Theactive region may be used to define the area where the gate or thesource/drain region of a transistor device is formed. Alternatively,some other terms, such as “oxide diffusion (OD) region,” “oxidedefinition (OD) area” and “active area,” may be used to refer to theactive region. The active region may be formed in various shapes from atop-view perspective, such as a rectangular shape, and may be sometimesreferred to as an “OD strip.” In some embodiments, the active region islaterally surrounded by a dielectric material, and thus the boundary ofthe active region is defined thereby. The active region may includedoped or undoped portions.

The present disclosure discusses a cell library characterizationframework for determining and providing the timing parameters of a cellin the design stage of manufacturing semiconductor ICs. When a synthesisoperation is used for implementing a circuit design, e.g., a circuitlayout or simply a layout, cell libraries are usually involved tosupport silicon-proven circuits of commonly used functional blocks forfacilitating the design process. The cell libraries may include avariety of standard cells with associated parameters characterizing theelectrical or geometrical characteristics of the cells from aquantitative perspective and serving as the cell profiles. Among thevarious cell parameters, the timing or delay parameters play a crucialrole for ensuing proper functioning of the circuit. For example, thetiming parameters associated with a pin of the cells, such as risedelay, fall delay or other transitional delays, affect the performanceand stability of signal sampling or signal transmission in which thecell is involved.

The timing parameters of a pin in a cell are provided in a timing tableor delay table for reflecting the actual time periods used by the pin ina fabricated chip. These timing parameters are dependent upon thedetailed design of the cell and thus are usually predetermined andprovided by the cell designer, e.g., a third-party library provider. Theactual time delays associated with the pin are further affected by thetopology of the circuit in the vicinity of the cell, or the circuitcoupled to the cell; such effect is referred to as the layout-dependenteffect. The layout-dependent circuit topology in the vicinity of a cell,or in the circuit features coupled to a cell, is collectively referredto as a context of a cell throughout the present disclosure. When morethan one cell of the same type is used in the layout, the individualcells may be referred to as different cell instances of that cell typethroughout the present disclosure.

To address the issue of the layout-dependent effect of a cell, thelibrary provider may assign more than one set of candidate timing tablesin the absence of information on the layout context, e.g., timing tablesthat cover fastest and slowest time delay conditions for a pin. The EDAtool may be executed to run multiple rounds of timing analysis tasksbased on the candidate timing table in each round. However, the designlayout is usually required to pass the timing verifications under atleast two timing tables providing the fastest and slowest delayconditions, and the fastest (or slowest) delay condition equally appliesto all cell instances in different locations of the layout withoutconsidering the layout contexts of individual cell instances. As aresult, the timing parameters provided for a specific cell instance maybe overly conservative or aggressive. A waste of area or power may occurdue to the overly conservative timing parameters, and reengineering maybe needed to modify the overly aggressive timing parameters. The chipperformance is thus limited.

In the present disclosure, an improved cell timing characterizationmethod and a system for implementing the method are proposed. Theproposed cell timing characterization is mainly comprised of two phases,i.e., a training phase and a recognition phase. During the trainingphase, a training model or classification model is built with themodel-specific parameters for classifying a variety of contexts of acell into different groups. The parameters may be trained for extractingthe correlation between the timing delays and the layout-dependenteffects for each group. For example, the training model may take intoaccount information of the layout features, e.g., the oxide diffusion(OD) regions, or equivalently, active regions, around the cell. Awell-trained model can be leveraged in the recognition phase, duringwhich a cell instance along with its context is classified by thetraining model into a suitable group and assigned a timing tableassociated with the group. Therefore, the proposed cell timingcharacterization method implements a context-aware timing parametercharacterization framework that can determine different timing tablesfor a cell instance by taking into account different layout contexts,and thus matches the actual time delay values better than thepredetermined timing tables. As a result, the estimated timing delayscan aid in improving the estimate of timing delays of the pins indifferent cell instances and reducing the likelihood of needing toreengineer the circuit due to the broad ranges of the delay valuesprovided by the timing tables. In addition, the burden of generating along list of timing tables for dealing with the layout-dependent effectis significantly reduced.

FIG. 1 is a schematic diagram illustrating a design flow 10 of asemiconductor integrated circuit (IC), in accordance with someembodiments. The design flow 10, employed for designing semiconductorICs or chips, utilizes one or more electronic design automation (EDA)tools to perform operations therein. A standalone computing device or acomputing cluster, such as a workstation, a personal computer or a groupthereof, is typically used in executing the method of the design flow10. The design flow 10 includes a system design stage 110, a logicdesign stage 120, a synthesis stage 130, a pre-layout simulation stage140, a placement and routing development stage 150, a parameterextraction stage 160, a timing analysis stage 165, a post-layoutsimulation stage 170, a photomask generation stage 190 and a circuitfabrication stage 195.

Initially, at the system design stage 110, a systematic architecture forthe chip of interest is provided with a high-level description. Duringstage 110, the chip functions along with performance requirements aredetermined according to a design specification. The chip functions areusually represented by respective schematic functional modules orblocks. In addition, an optimization or performance trade-off may besought to achieve the design specification at acceptable levels of costand power.

At the logic design stage 120, the functional modules or blocks aredescribed in a register transfer level (RTL) using a hardwaredescription language. Commercially available language tools aregenerally used, such as Verilog or VHDL. In an embodiment, a preliminaryfunctionality check is performed during stage 120 to verify if theimplemented functions conform to the specification set forth in stage110. In some embodiments, a timing verification is performed todetermine if the RTL-level circuit design complies with thespecification.

Subsequently, at the synthesis stage 130, the modules in the RTLdescriptions are converted into an instance of design data, e.g.,netlist data, where the circuit structure, e.g., logic gates andregisters, of each function module are established. In an embodiment, alibrary 132, e.g., a standard cell library, is provided to supplydifferent classes of low-level circuits, i.e., standard cells, servingspecific Boolean logic or sequential logic functions. In someembodiments, technology mapping of logic gates and registers toavailable cells in the standard cell libraries are conducted. Further,the design data or netlist data is provided to describe the functionalrelationship of the chip at a gate level. The library 132 may beprovided by an IC designer, an IC manufacturing company, an EDA toolprovider or any relevant third party. The library 132 also provides theparameters associated with each cell, such as the timing delays, powers,voltages, and the like. In an embodiment, the netlist data istransformed from the gate-level view to a transistor-level view. In anembodiment, when the library is provided or updated (as will bedescribed in subsequent paragraphs herein) and incorporated into the EDAtool, the IC designer can identify violations of the design rule (e.g.,timing violations) and revise the original netlist data in response tothe identified violations.

Subsequently, the gate-level netlist data is verified at the pre-layoutsimulation stage 140. During the verification process of stage 140, ifsome functions fail the verification in the simulation, the design flow10 may be paused temporarily or may go back to stage 110 or 120 forfurther modification. After the pre-layout simulation stage 140, thechip design has passed a preliminary verification and the front-enddesign process is completed. Next, a backend physical design process isconducted. In some embodiments, a timing verification is also performedto determine if the synthesized netlist data complies with thespecification.

During the placement and routing stage 150, a physical architecturerepresenting the chip, determined during the front-end process, isimplemented. Although not stated expressly, the layout development mayinclude a floorplan stage in the beginning of or prior to the placementand routing stage 150, in which the floorplan stage is used forallotting spaces for major functional blocks in a two-dimensionalcircuit plane. Subsequently, the layout development involves a placementoperation and a routing operation in sequence. Detailed structures andassociated geometries for the components of the major blocks in thefloorplan stage are determined in the placement operation. Interconnectsamong different components are routed subsequent to the placementoperation. Both placement and routing operations are performed to meetthe requirement of a design rule check (DRC) deck so that themanufacturing constraints of the chip are fulfilled. In an embodiment, aclock tree synthesis operation is performed at the placement and routingstage for a digital circuit in which clock generators and circuits areincorporated into the design. In an embodiment, a timing analysis orverification operation is performed to determine whether the tentativecircuit arrangements meet the design specification, and a post-routingoperation is performed subsequent to the preliminary routing operationin order to resolve timing issues discovered during the timingverification operation. Once the placement and routing stage 150 iscompleted, a placed-and-routed layout is created and a netlist alongwith data on placement and routing is generated accordingly.

During the parameter extraction stage 160, a layout parameter extraction(LPE) operation is conducted to derive layout-dependent parameters, suchas parasitic resistance and capacitance, based on the layout developedin the placement and routing stage 150. Subsequently, a post-layoutnetlist data, which includes the layout-dependent parameters, isgenerated.

Subsequently, timing analysis or timing verification is performed at atiming analysis stage 165. The timing verification performed in stage165 may take into account the layout-dependent parameters extracted instage 160, and better reflect the circuit behavior under the effects ofparasitic resistance and capacitance. The library 132 may be involved inthe timing analysis operation of stage 165.

During the post-layout simulation stage 170, a physical verification isperformed, taking into consideration the parameters acquired in previousstages. A simulation of transistor-level behavior is conducted toexamine whether the chip performance derived by the post-layout netlistmeets the system specifications. In some embodiments, the post-layoutsimulation is performed to minimize probability of electrical issues orlayout difficulties during the chip manufacturing process. In anembodiment, the library 132 is provided not only for stage 130, but alsofor stages 140, 150, 160, 165, and 170 so that the electrical orgeometric parameters of cells and other features listed in the library132 can be leveraged to emulate the real-world performance of thecircuits throughout the design flow 10.

Next, in stage 180, it is determined whether the post-layout netlistmeets the design specifications. If the result of the post-layoutsimulation is unfavorable, the design flow 10 loops back to previousstages for tuning functionalities or structures. For example, the designflow 10 may loop back to stage 150 where the layout is re-developed toresolve issues from a physical perspective. Alternatively, the designflow 10 may retreat to an earlier stage 110 or 120 to recast the chipdesign from a functional level in case the problems cannot be resolvedwithin the back-end process.

If the post-layout netlist passes the verification, the circuit designis accepted and then signed off accordingly. The chip is manufacturedaccording to the accepted post-layout netlist. In an embodiment, duringstage 190, at least one photomask is generated based on the verifiedpost-layout netlist in stage 170. A photomask is a patterned mask usedto allow a portion of light to pass through or reflect off the photomaskwhile blocking or absorbing other portions of the light in order to forma pattern of features on a light-sensitive layer, e.g., a photoresistlayer, on a wafer. The photomask is used to transfer the patterns of theverified post-layout netlist onto wafers. In some embodiments, amulti-layer layout netlist may require a set of photomasks in which thefeature pattern in each layer is established in the correspondingphotomask. As a result, the patterns of the layout netlist formed on thephotomasks are transferred to the light-sensitive layer through anexposure operation.

During stage 195, the circuit is fabricated on the wafer using thepatterns on the photomasks generated in stage 190. The fabrication mayinvolve known semiconductor manufacturing operations, such aslithography, etching, ion implantation, deposition, and thermaloperations. In some embodiments, a testing operation may be utilized inan intermediate or final phase of stage 195 to ensure physical andfunctional integrity of the fabricated circuit. In some embodiments, asingulation operation may be used to separate the circuit wafer intoindividual circuit dies. The fabrication of the circuit is thuscompleted.

The design flow 10 illustrated in FIG. 1 is exemplary. Modifications tothe above-mentioned stages, such as changes of order of the stages,partition of the stages, and deletion or addition of stages, are withinthe contemplated scope of the present disclosure.

FIG. 2 is a schematic diagram of a context grouping process 200, inaccordance with some embodiments of the present disclosure. The contextgrouping process 200 is used to provide classified groups of a targetcell based on their layout contexts. When the context grouping process200 begins, at least one layout 202 is accessed or generated thatincludes at least one cell instance Ci. The layout 202 may be historicallayout data generated at different stages of the backend phase, such asstage 150, 160, 165, 190 or 195 with different level of completeness. Insome embodiments, the layout 202 is formed of a plurality of layoutswhere the layout contexts in the vicinity of the cells are determined.For example, the layout context for the cell instance Ci comprisesinterconnections of resistors, capacitors, inductors, metal lines, andthe layout context may be formed of features, such as oxide diffusion(OD) regions (or active regions), gate regions, dielectric regions,doping regions and conductive regions, that are adjacent to the cellinstance Ci. In some embodiments, a context zone defining the boundariesof a layout context for a cell instance is predetermined, and only thecircuit features of the layout that overlaps the context zone areconsidered as the content of the context. In some embodiments, thecontext zone has a circular shape, a polygonal shape such as arectangular shape, or other suitable shape.

In some embodiments, a simulation is performed to measure or simulatethe timing delays of the individual cell instances in the layout ofinterest. The simulation is conducted across an entire layout or apartition of the layout by taking into account the context informationof each cell instance. The simulated timing delays of the cell instancesare different according to different cell contexts and may be used asthe timing delays of the respective cell instances in a timing analysisor timing verification operation.

A training model 204 is provided to classify the historical orpre-determined contexts of the cell instance Ci in the layout data 202into different groups through the context grouping process 200 based ona model setting 203. In some embodiments, abstracted information of thelayout 202, such as complied parameters of the layout 202, is fed intothe training model 204. In some embodiments, the circuit topology in thevicinity of a cell may be transformed into one or more vicinity imagesand the vicinity images are fed into the training model 204. In someembodiments, all cell instances Ci's of the same cell type areidentified by the training model 204. Further, the layout contextsincluding the circuits around the identified cell instances Ci's areextracted and fed into the training model 204.

The training model 204 is configured to conduct context grouping underan artificial intelligence or machine learning framework. The trainingmodel 204 is defined by a model structure and the accompanying modelsetting 203. In some embodiments, the model setting 203 may include themodel type, the hierarchy of the models including the layers, nodes,interconnections and learning algorithms, the number of groups N with Nbeing an integer, and the set of timing (delay) tables for each of thegroups. The model type of the training model 204 may be an artificialneural network including, but not limited to, convolutional neuralnetwork (CNN), recurrent neural network (RNN), autoencoder, and thelike. In some embodiments, the training model 204 is constructed byLeNet, AlexNet, VGG, GoogLeNet, ResNet, and the like. In someembodiments, the model setting 203 further includes, but is not limitedto, the number of layers for the training model 204, the node number ofeach layer, and the weight values of edges interconnecting the nodes. Insome embodiments, the model training process is performed using anunsupervised learning approach.

The training model 204 is trained by the layout information of thelayout 202, specifically the circuit topology information, or context,of the cell instance Ci. The context for the cell instance Ci mayinclude active regions (or equivalently OD strips), gate regions,dielectric regions, doping regions and conductive regions, in which theshapes, orientations and distances of the aforesaid regions may affectthe timing delays of the pins of the cell instance Ci. In some otherembodiments, the context for the cell instance Ci includes resistors,capacitors, inductors and metal lines that affect the response time ortransmission time of a signal. The configurations, geometries andmaterials of these features may determine the electrical properties,such as capacitance, inductance and resistance seen or experienced bythe cell instance Ci from a pin of the cell instance Ci.

FIG. 3A is an exemplary layout 202, in accordance with some embodimentsof the present disclosure. In the depicted embodiment, the layout 202includes at least six cell rows extending horizontally, in which thecell rows may have the same or different row heights. In addition, eachcell row includes cells (e.g., ten cells in the depicted embodiment)spaced apart from one another by a predetermined distance. Each cell rowof the layout 202 further includes active regions (also referred to asOD strips) extending horizontally. In the depicted embodiment, each cellrow includes a top active region strip extending over the cells, abottom active region strip extending below the cells, and two middleactive region rows across the cells. It should be noted, however, thatalthough the general configurations of the cells with respect to theactive region strips look similar in FIG. 3A, the detailed abuttingconditions of each cell with its neighboring active region strips mayvary. The subtle differences of the contexts among different cellinstances lead to the variation of timing delays. In the proposedframework, cell instances with the same cell type are identified,collected and treated individually. For example, exemplary cellinstances 302A and 302B are identified that serve as two instances ofcell 302 in the layout 202. The number and the configurations of theactive region strips in FIG. 3A are shown for illustrative purposesonly. Other configurations are also within the contemplated scope of thepresent disclosure.

FIGS. 3B to 3E are various exemplary layouts contexts of a cell, inaccordance with some embodiments of the present disclosure. Referring toFIG. 3B, a layout 310 comprising six active region strips and six gatestrips is formed by several cells abutting one another. A cell 302A islocated at the center of the layout 310, and other cells, such as cells303, 304, 305 and 306, are disposed to surround the cell 302A. Theaforesaid cells are arranged to implement a plurality of parallel gatestrips and parallel active region strips of the layout 310. The parallelgate strips may extend in a direction different from the direction inwhich the parallel active region strips extend. In some embodiments, thegate strips are substantially perpendicular to the active region strips.Each of the cells 303, 302A and 304 includes a first portion, a secondportion and a third portion of a gate strip G1, respectively, in whichthe three portions constitute a contiguous gate strip across theboundaries of the cells 302A, 303 and 304. Further, some cells in thelayout 310 include a respective portion of an active region strip, e.g.,each of the cells 305, 302A and 306 includes respective portions of anactive region strip OD1 or OD2 and these portions constitute acontiguous active region strip across the boundaries of the cells 305,302A and 306.

In some embodiments, the dimensions and locations of the active regionstrips around the cell 302A affect the timing delay characteristics ofthe cell 302A. For example, lengths L11 and L12 of the active regionstrip OD1 are included in the parameters of the context of the cell302A, in which the length L11 is measured from a left boundary side ofthe active region strip OD1 to the gate strip G1 and the length L12 ismeasured from a right boundary side of the active region strip OD1 tothe gate strip G1. Similarly, lengths L21 and L22 of the active regionstrip OD2 are considered as parameters of the context of the cell 302A,in which the length L21 is measured from a left boundary side of theactive region strip OD2 to the gate strip G1 and the length L22 ismeasured from a boundary right side of the active region strip OD2 tothe gate strip G1.

Referring to FIG. 3C, a layout 320 is formed of several cells includingthe cell 302A located at the center of the layout 320. Theconfigurations of the constituent cells arranged to implement the gatestrips and active region strips are similar to those in FIG. 3B and, forsimplicity, are not separately illustrated in FIG. 3C. In someembodiments, the layout 320 further includes a well region W1overlapping at least some of the gate strips or active region strips.The well region W1 may be also an implantation region or a dopingregion. The well region W1 may be formed across several cells, such ascells 303, 305, 306 and 304. In the depicted embodiment, the well regionW1 has an area greater than the area of the cell 302A and overlaps theentire cell 302A. In some embodiments, the well region W1 is arranged ina layer of the cell 302A same as or different from the layer of the cell302A in which the gate strips or the active region strips reside.

In some embodiments, the dimensions and locations of the well region W1around the cell 302A affect the timing delay characteristics of the cell302A. For example, distances between the boundary of the well region W1and the features in the cell 302A are included as parameters for acontext-aware timing calculation framework. To be specific, distances D1and D2 are included as parameters of the context of the cell 302A, inwhich the distance D1 is measured from an upper boundary side WS1 of thewell region W1 to the active region strip OD1 in the cell 302A and thedistance D2 is measured from a lower boundary side WS2 of the wellregion W1 to the active region strip OD1. Similarly, distances D3 and D4are included as parameters of the context of the cell 302A, in which thedistance D3 is measured from a left boundary side WS3 of the well regionW1 to the gate strip G1 in the cell 302A, and the distance D4 ismeasured from a right boundary side WS4 of the well region W1 to thegate strip G1.

Referring to FIG. 3D, a layout 330 is formed of several cells includingthe cell 302A located in a center of the layout 330. The configurationsof the constituent cells arranged to implement the gate strips andactive region strips are similar to those in FIG. 3B and, forsimplicity, are not separately illustrated in FIG. 3D. In someembodiments, the dimensions and locations of the gate strips adjacent tothe cell 302A, such as gate strips G2, G3, G4 and G5, affect the timingdelay characteristics of the cell 302A. For example, spacing values S12and S13 are included as parameters of the context of the cell 302A, inwhich the spacing S12 is defined as spacing between the gate strips G1and G2 while the spacing S13 is defined as spacing between the gatestrips G1 and G3. Similarly, spacing values S24 and S35 are included asparameters of the context of the cell 302A, in which the spacing S24 isdefined as spacing between the gate strips G2 and G4 and the spacing S35is defined as spacing between the gate strips G3 and G5.

FIG. 3E is a schematic cell matrix 340 having entries of various cellinstances with associated cell contexts with respect to the cell 302 ofFIG. 3A. Each entry of the cell matrix 340 is represented by a cellcontext 311 to 319. Only active region strips around the cell 302 areshown in the entries. The configurations of the constituent cellsarranged to implement the active region strips are similar to those inFIG. 3B and, for simplicity, are not separately illustrated in FIG. 3E.The layout context in each entry includes the same number of activeregion strips but includes different contexts. For example, the topactive region strip has different configurations: the top active regionstrip is absent from over the cell 302 in the context 311; the topactive region strip extends over the cell 302 in the contexts 313, 314and 317 with various opening widths and locations; and the top activeregion strip is continuously over the cells 302 in the contexts 312,315, 316, 318 and 319. In other scenarios, the two middle active regionstrips are in direct contact with (or spaced by a distance less than apredetermined value S1 from) the boundary of the cell 302 on both sidesin the contexts 311, 312 and 313; the two middle active region stripsare spaced apart from (or spaced by a distance equal to or greater thana predetermined value S2 from) the cell 302 on only one side in contexts314, 315 and 316; and the two middle active region strips are spacedapart from (or spaced by a distance equal to or greater than thepredetermined value S2 from) the cell 302 on both sides in contexts 317,318 and 319. Further, the two middle active region strips are spacedapart from the cell 302 on two sides by substantially equal distances S3in contexts 319 yet by disparate distances S4 and S5 (where at least oneof S4 and S5 is greater than S2 in some embodiments) in contexts 317 and318. In some embodiments, the conditions of the active region strip areincluded in the parameters of the context of the cell 302, e.g., whetherthe active region strip adjacent to the cell 302 contacts the cell 302,or whether the active region strip is spaced apart from the cell 302 onone side or two sides, or the lateral distance between the cell and itsnearest active region strip.

FIG. 3F is a schematic diagram of the training model 204, in accordancewith some embodiments of the present disclosure. Referring to FIG. 2 andFIG. 3F, the training model 204 provides a training result of contextgrouping. The training model 204 has a structure constructed of aplurality of neurons (nodes) 521 interconnected through edges 322. Theplurality of nodes may form various layers, e.g., an input layer 324comprising input nodes 321, an output layer 326 comprising output nodes323 and one or more hidden layers 328 comprising hidden nodes 325.Parameters of the training model 204 may also be determined, such as thenumber of nodes in each of the input layer 324, the output layer 326 andthe hidden layers 328, and the interconnection topology of the edges322. In an embodiment, the output layer 326 may include a single outputnode 323. In the present embodiment, one or more layouts 202 including amultitude of cell instances Ci and the associated contexts is fed intothe training model 204 to trigger the machine-learning procedure. Insome embodiments, the input nodes 321 receive the parameters of theactive region strips of the layout, such as the number of active regionstrips, the strip configuration index (e.g., indices representing thecases of fully covering the cell, partially covering the cell, absentfrom the cell, abutting or spaced, and the spaced distances) of eachactive region strip. In some other embodiments, the input nodes 321receive the parameters of distances or spacing values with respect tothe active region strips or gate strips in FIGS. 3B to 3E, such as thelengths L11, L12, L21 and L22, the distances D1 through D4 and thespacing values S12, S13, S24 and S35. In some embodiments, the outputnodes 323 provide the parameters associated with each group. Iterativetraining procedures for the hidden layers 328 are performed until thevalues of the hidden nodes 325 attain converged values.

Other types of the training model 204 are also applicable. In someembodiments, a pattern recognition-based training model 204 receives theraw schematic of the two-dimensional layout comprised of polygonalfeatures and is configured to conduct pattern recognition and generate atraining result in response to a training condition, e.g., aclassification group number, without extracting further parameters. Insome embodiments, a bonding zone with a radius or circumference isdetermined within which the two-dimensional polygons are considered bythe training model 204.

Referring back to FIG. 2 , upon completion of the training process, thetraining model 204 provides a set of well-trained model parameters 206and a group data 208 serving as a result of the context grouping, inwhich the group data includes a plurality of context groups of the cellCi, such as Group 1, Group 2, . . . , Group N, in which each contextgroup in the group data 208 comprises classified contexts or circuittopologies. In addition, the context grouping process 200 provides adatabase 210 including timing tables, such as timing table TT1, timingtable TT2, . . . , timing table TTN, corresponding to the context groupsin the group data 208. In some embodiments, more than one timing tableis provided to correspond to one context group in the group data 208,e.g., each context group is associated with a set of timing tables. Insome embodiments, the values of timing delays entered in each timingtable are obtained from a timing simulation. In some embodiments, if thedistribution of the simulated timing delays of a context group exhibitsa smaller deviation (i.e., has values grouped more closely together) ascompared to the timing delays of the entire population of cellinstances, the training process 200 is considered convergent andsuccessful. The model parameters 206, the group data 208 and thedatabase 210 are to be included in the library 132 in FIG. 1 .

In some embodiments, the library 132 includes group identifierscorresponding to the timing tables TT1, TT2 and TTN. In someembodiments, each group identifier is associated with more than onetiming table for the context groups. In some embodiments, the groupidentifier can be accessed by the layout 202 and used to indicate whichcontext group a cell instance in the layout 202 belongs to.

FIG. 4A is a schematic diagram of a result of the context grouping, inaccordance with some embodiments of the present disclosure. The resultis provided by the context grouping process 200 and is represented bythe group data 208. In some embodiments, the context grouping isconducted based on the cell matrix 340 collected from the layout 202. Inthe depicted embodiment, the group number is set at four; however, othervalues of group number may be applicable dependent upon designrequirements. The context grouping operation generates four contextgroups 401, 402, 403 and 404 represented by the contexts 312; 311 and313; 314, 315 and 316; and 317, 318 and 319, respectively. In someembodiments, the contexts 311 through 319 are classified into thecorresponding groups 401 through 404 by the training model 204 based ona cost function of minimizing the timing delay differences within thegroups, and the training model 204 is trained to store the correlationbetween the cell timing delays and their topologies in the modellearning hierarchy, e.g., the weights of the edges 322 in the trainingmodel 204 of FIG. 3F.

FIG. 4B is a schematic diagram of a chart 400 displaying timing delaydistributions of the context groups in FIG. 4A, in accordance with someembodiments of the present disclosure. In an embodiment, a distributionof fall delay values (other types of timing delays also apply but mayexhibit different distribution profiles) of the cell 302, obtained by atiming simulation on the database 210, is shown in the order of contextgroup. The X-axis represents a cell instance index and the Y-axisrepresents the delay values. It can be seen in FIG. 4B that the delayvalues of each group are concentrated or clustered, and each group issubstantially separated from one other. That means the timing delaydistributions of a cell can be successfully classified into groups offiner timing delay ranges based on the layout contexts of individualcell instances.

In some embodiments, the timing delays in each context group 401, 402,403 or 404 are obtained from actual delay values of the cell 302 in oneor more layout data that have met the requirements of timingverification. In some embodiments, the timing delays in each contextgroup 401, 402, 403 or 404 are obtained from actual delay values of thecell 302 in a fabricated circuit or are obtained through a simulationfor the layout 202. In some embodiments, the timing table for thecontext group 401, 402, 403 or 404 as derived from the component cellsof the respective context group is associated with a group identifier.The group identifier can be used to indicate the context group of a cellinstance.

In some embodiments, the simulated delay values of a cell instance inthe respective context group are determined as the best-case orworst-case delay values of that context group. For example, thesimulated delay value of the cell 302 with respect to the context 312 isdetermined as the representative delay value in the timing tableassociated with the context group 401. In some embodiments, the delayvalues in the timing tables, e.g., TT1 through TTN in FIG. 2 , for thecorresponding context group in database 210 are determined based on theclustered delay values in the respective context group. For example, abest-case delay value T1, which is around the minimum of the delayvalues in the context group 404, and a worst-case delay value T2, whichis around the maximum of the delay values in the context group 404, aredetermined as representative delay values in the best-case andworst-case timing tables, respectively, associated with the contextgroup 404. Similarly, a best-case delay value 12 and a worst-case delayvalue T3 are determined as representative delay values in the best-caseand worst-case timing tables, respectively, associated with the contextgroup 403. A best-case delay value T3 and a worst-case delay value T4are determined as representative delay values in the best-case andworst-case timing tables, respectively, associated with the contextgroup 402. A best-case delay value T4 and a worst-case delay value T5are determined as representative delay values in the best-case andworst-case timing tables, respectively, associated with the contextgroup 401. In some embodiments, the designation of the worst-case delayvalue and the best-case delay value of a context group are swapped indifferent applications. As such, during a timing verification operationfor a best-case scenario (or, alternatively, a worst-case scenario),each cell instance is assigned the respective best-case delay valuesassociated with the context group, and the timing analysis is performedbased on the assigned delay values of individual cell instances.

In some embodiments, the representative delay value for a context groupthat includes the best-case scenario and the worst-case scenario isdetermined based on the delay values of all cells in the respectivecontext group during the context grouping process 200. Taking thecontext group 401 as an example, the representative delay valuecorresponding to the context group 401 is obtained as an arithmeticaverage or a geometric average of the delay values of all the cellinstances in the context group 401.

Existing methods of assigning timing tables for a cell usually determinea best-case delay value, e.g., T1, and a worst-case delay value, e.g.,T5, as the two representative timing delays in the absence of layoutcontexts. It is clearly seen that the range between delay values T1 andT5 is larger than the delay value ranges of each of the context groups.However, as discussed previously, a large gap is observed between theactual timing delays and any of the two delay bounding values T1 and T5for each of the cell instances, since the values T1 and T5 aredetermined conservatively. The fixed delay values T1 and 15 may notcover the individual delay value adaptively, leading to unnecessaryoperations of revising the layout 202 or the further steps ofengineering change order (ECO) steps. Extra resources of chip area andpower, and sacrificed chip performance for such layout revision, willcompromise the improvement gained from other endeavors for enhancing thecircuit performance. In contrast, the proposed training model 204 canassign tailored timing delays of a cell instance based on a set oftiming delay groups by leveraging the layout context around that cell inta instead of blindly assigning a one-size-fits-all timing table to allcell instances. The timing delay assignment can be conductedsuccessfully with the help of the training model 204 based on thecontexts in the timing-verified layouts.

FIG. 5 is a schematic diagram 500 of a context-aware cell recognitionalgorithm, in accordance with some embodiments of the presentdisclosure. Initially, a layout is accessed at stage 502. In someembodiments, the layout is an intermediate-state layout formed duringthe design flow 10, such as a layout at the stage 130, 150 or 160. Insome embodiments, the layout is accessed subsequent to a synthesisoperation and prior to a placement and routing operation. In someembodiments, the layout under development as provided at stage 502,which has not partly or fully passed the timing analysis, is differentfrom the timing-verified layout 202 provided in the training phase,which has been proven to be compliant with the timing constraint rule.The layout may be constructed of various kinds of cells in which each ofthe cells may be applied in more than one instance.

At stage 504, a layout topology pattern extraction operation isperformed to collect layout contexts of a certain cell. The parametersof the context are provided to a context-aware cell recognition engineat stage 506. In some embodiments, the context-aware cell recognitionengine performs cell classification based on an artificial intelligencecell recognition machine, such as convolutional neural network (CNN),recurrent neural network (RNN), autoencoder and the like. In someembodiments, the context-aware cell recognition engine is constructed byLeNet, AlexNet, VGG, GoogLeNet, ResNet, and variants thereof. In someembodiments, the cell recognition machine has a same model type andmodel structures as those in the training process 200 so that theparameters trained by the training model 204 can be incorporated in thestage 506. In some embodiments, the library 132 in FIG. 1 provides thewell-trained parameters required for the context-aware cell recognitionengine, such as the model type of the learning machine, and itsassociated configurations including the number of stages, the number ofnodes, and the weights of the interconnecting edges. In someembodiments, the library 132 also provides the number of context groupsfor the cell recognition and the timing tables for each context group.During operation, the context grouping procedure at stage 506 proceedsuntil the recognition of all the cell instances with respect to aspecific cell type and all of the cell types are completed.

Subsequently, at stage 508, at least one timing table is selected to thecell instance, and is recognized and grouped by the context-aware cellrecognition engine at stage 506. At this time, the layout is updated inwhich each cell instance is determined to associate with the at leastone selected timing table. In some embodiments, one context group withmore than one timing table is selected for one cell instance. Forexample, a best-case timing table and a worst-case timing table areselected to be associated with one context group.

In some embodiments, the layout includes or is associated with a map oftiming tables. In the map, a timing table is referred to a groupidentifier. In some embodiments, the layout includes a group identifierwhich indicates the selected timing table for a cell instance. In someembodiments, a group identifier for a cell instance is referred to by aset of timing tables.

At stage 510, a delay value for the cell instance is determined from theselected timing table. As discussed previously, each cell instance maybe assigned a best-case timing table or a worst-case timing table oncethe context group is selected. In some embodiments, the delay value of apin in a cell instance is further determined based on the actualparameter values in the layout context. In such circumstance, once it isdetermined that a cell instance belongs to a certain context group, atiming table is provided which includes an array of delay values.

FIG. 5B shows a diagram illustrating the stage 510 in which a delayvalue is determined by selection from a selected timing table 526, inaccordance with some embodiments of the present disclosure. In thedepicted example, the timing table 526 may be the timing table TT1, TT2or TTN in the database 210 obtained through the training process 200.The timing table 526 may represent various types of delays, such as afall delay, a rise delay, a transition delay, or the like. In someembodiments, a context group may be associated with multiple timingtables 526 with entries of various delay types.

The timing table 526 may correspond to a best-case scenario or aworst-case scenario and include an array of delay values based onvarious values of table entries. In some embodiments, the table entriesare extracted from an electrical network, such as effective capacitance,effective inductance, effective resistance, or combinations thereofcoupled to the input/output nodes of the cell instance. In someembodiment, the table entries are obtained through electricalsimulations of the cell, such as the slew rate of the input current. Insome embodiment, the table entries are obtained from both of thetopology of the electrical networks and the simulation of the cell. Insome embodiment, the table entries may be provided by the library 132.FIG. 5B shows that timing table 526 is constructed based on a firsttable entry P with three values P11, P12 and P13, and a second tableentry Q with three values Q11, Q12 and Q13. The dimensions of the timingtable 526 are determined by the sizes of the table entries P and Q. Thetable entries P and Q may represent effective capacitance and effectiveresistance on the input/output nodes of the cell instance. The selectionof the delay value from the timing table 526 is conducted based on acombination of the values of the table entries P and Q. For example, ifit is determined that a cell instance is coupled to a network formed ofa capacitance P1 and a resistance Q2, the representative delay value isselected as the entry T21. In some embodiments, if the actual values forthe table entries for the cell are not identical to the contextparameter values provided in the timing table 526, the representativedelay value is determined by interpolation or extrapolation based on theentries in the timing table 526. As a result, a quantity-based delayvalue determination for a cell instance on top of the context-awarecontext grouping further aids the performance of the timing delaycharacterization.

At stage 512, a timing analysis is performed against the updated layoutusing a timing analysis engine. During the stage 512, it is determinedwhether the timing behavior, such as the setup time and hold time, ofeach timing path complies with the predetermined timing constraint rule.A timing report is provided or generated at stage 514 and includes theresults of the timing analysis as to whether the layout complies withthe timing verification performed in stage 512.

FIG. 6 is a flowchart of a method 600 of a context-aware cellrecognition algorithm, in accordance with some embodiments of thepresent disclosure. At step 602, a layout of an integrated circuit (IC)is accessed. The layout includes at least one cell. At step 604, a setof context groups with corresponding timing tables for the cell areprovided. In some embodiments, the context groups and the timing tablesare provided through a library. The timing tables of each context groupstored in the library may be obtained through a timing simulation on oneor more representative cells of the respective group in whichlayout-dependent effects (i.e., effects caused by the layout context) ofthe representative cell are considered.

At step 606, a context group and a corresponding timing table aredetermined (that includes being selected and assigned) for the cellbased on a context of the cell or a circuit topology in the vicinity ofthe cell. The context group is associated with the timing table. In someembodiments, the determined context group is selected from the set ofcontext groups provided by the library. In some embodiments, a groupidentifier of the timing tables provided by the library and associatedwith the determined context group is assigned to the cell.

At step 608, a delay value for the cell is determined from thedetermined timing table based on the timing table entries. In someembodiments, the table entries may include context parameters, such ascapacitance, inductance, resistance or other electrical characteristics.In some embodiments, the delay values are selected from a look-up table.The delay values are determined from a plurality of look-up tables(timing tables) given the table entries as inputs.

At step 610, a timing analysis is performed on the layout to determinewhether the layout complies with a timing constraint rule. Ifaffirmative, the layout passes the timing verification and the method600 proceeds with subsequent steps, such as step 614 in which apost-layout simulation is performed. In some embodiments, the step 614further includes transferring a pattern of the layout to a photomask inresponse to determining that the layout complies with the timingconstraint rule in step 612. In some embodiments, the step furtherincludes fabricating the IC according to the pattern of the photomask.

If it is determined that the layout fails the timing verification, e.g.,there exists at least one cell or one timing path that fails to complywith the timing constraint rule, the method 600 proceeds with step 616and returns to the preceding stages, such as the synthesis stage 130,the floorplan stage, or the placement and routing (P&R) stage 150, forrevising the layout.

FIG. 7 is a schematic diagram of a system 700 implementing layoutdesigns, in accordance with some embodiments. The system 700 includes aprocessor 701, a network interface 703, an input/output (I/O) device705, a storage 707, a bus 708 and a memory 709. The bus 708 couples thenetwork interface 703, the I/O device 705, the storage 707, the memory709 and the processor 701 to each other.

The processor 701 is configured to execute program instructions thatinclude a tool configured to perform the method as described andillustrated with reference to figures of the present disclosure.Accordingly, the tool is configured to execute the steps such as:receive design specifications and a library, perform a pre-layoutsimulation, generate a design data for a layout, perform layoutaccessing, determine a parameter of timing of the library, perform amodel training algorithm, determine a plurality of timing tables, updatethe library, perform operations of placement and routing, perform LVS,generate a consolidated netlist by incorporating the parameters, performcontext grouping tasks and assign a timing table for cell instances inthe layout, perform post-layout simulation, and verify the post-layoutsimulation result.

The network interface 703 is configured to access program instructionsand data accessed by the program instructions stored remotely through anetwork (not shown).

The I/O device 705 includes an input device and an output deviceconfigured for enabling user interaction with the system 70. In someembodiments, the input device includes, for example, a keyboard, a mouseand other devices. The output device includes, for example, a display, aprinter and other devices.

The storage 707 is configured for storing program instructions and dataaccessed by the program instructions. In some embodiments, the storage707 includes a non-transitory computer readable storage medium, forexample, a flash memory, a magnetic disk, an optical disk or the like.

The memory 709 is configured to store program instructions to beexecuted by the processor 701 and data accessed by the programinstructions. In some embodiments, the memory 709 includes anycombination of a random access memory (RAM), some other volatile storagedevice, a read only memory (ROM), and some other non-volatile storagedevice.

In accordance with one embodiment of the present disclosure, a method isperformed by at least one processor. A layout of an integrated circuit(IC) is accessed, wherein the layout has at least one cell. A contextgroup for the cell is determined based on a layout context of the cell,wherein the context group is associated with a timing table. A timinganalysis is performed on the layout to determine whether the layoutcomplies with a timing constraint rule according to the timing table.

In accordance with another embodiment of the present disclosure, asystem includes one or more processors and one or more programs havinginstructions which, when executed by the one or more processors, causethe system to perform the following steps. A layout of an integratedcircuit (IC) is accessed, wherein the layout has a cell. A context groupfor the cell is determined based on a layout context of the cell,wherein the context group is associated with a timing table. A timinganalysis is performed on the layout to determine whether the layoutcomplies with a timing constraint rule according to the timing table.

In accordance with another embodiment of the present disclosure, anon-transitory computer readable storage medium includes instructionswhich, when executed by a processor, perform the following steps. Alayout of an integrated circuit (IC) is accessed, wherein the layout hasa cell. A context group for the cell is determined based on a layoutcontext of the cell, wherein the context group is associated with atiming table. A timing analysis is performed on the layout to determinewhether the layout complies with a timing constraint rule according tothe at least one timing table.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A method, performed by at least one processor,comprising: accessing a layout of an integrated circuit (IC), the layoutcomprising a cell; recognizing a representative context group for thecell from a set of context groups based on a layout context of the cellin the layout, the representative context group being associated with arepresentative timing table different from timing tables of remainingcontext groups in the set of context groups; and performing a timinganalysis on the layout to determine whether the layout complies with atiming constraint rule according to the representative timing table. 2.The method of claim 1, comprising transferring a pattern of the layoutto a photomask in response to determining that the layout complies withthe timing constraint rule.
 3. The method of claim 2, further comprisingfabricating the IC according to the pattern of the photomask.
 4. Themethod of claim 1, wherein the layout context is formed of at least oneof an active region strip, a gate strip, a dielectric region, a dopingregion and a conductive region.
 5. The method of claim 4, wherein therecognizing of the representative context group for the cell comprisesrecognizing the representative context group based on whether the activeregion strip contacts the cell.
 6. The method of claim 1, wherein thelayout comprises a gate strip in the cell and a well region overlappingthe cell, and the representative context group is recognized based on adistance between a boundary side of the well region and the gate strip.7. The method of claim 6, wherein the layout further comprises an activeregion strip in the cell, and the representative context group isrecognized further based on a distance between a boundary side of thewell region and the active region strip.
 8. The method of claim 1,wherein the layout comprises a first gate strip, the layout contextcomprises a second gate strip adjacent to the cell, and therepresentative context group is recognized based on a distance betweenthe first gate strip and the second gate strip.
 9. The method of claim1, further comprising providing the set of context groups withcorresponding timing tables for the cell from a library.
 10. The methodof claim 9, further comprising performing a training operation on aclassification model to provide the set of context groups.
 11. Themethod of claim 10, wherein the training operation is performed based onanother layout that passes a timing verification.
 12. The method ofclaim 10, wherein the classification model is characterized by an inputlayer, an output layer, at least one hidden layer, and weights of edgesinterconnecting nodes of the input layer, the output layer and the atleast one hidden layer.
 13. The method of claim 1, wherein the layoutcomprises an identifier indicating the identity of the recognizedrepresentative context group.
 14. The method of claim 1, furthercomprising determining a delay value from the representative timingtable for the cell based on context parameters of the representativetiming table.
 15. The method of claim 1, further comprising performing aplacing-and-routing operation on the layout prior to accessing thelayout.
 16. A system, comprising one or more processors and one or moreprograms including instructions which, when executed by the one or moreprocessors, cause the system to: access a layout of an integratedcircuit (IC), the layout comprising a cell; recognize a representativecontext group for the cell from a set of context groups based on alayout context of the cell in the layout, the context group beingassociated with a representative timing table different from timingtables of remaining context groups in the set of context groups; andperform a timing analysis on the layout to determine whether the layoutcomplies with a timing constraint rule according to the representativetiming table.
 17. The system of claim 16, wherein the instructionswhich, when executed by the one or more processors, further cause thesystem to perform a context grouping operation on the cell based on thelayout context, a group number of the context groups and a set of timingtables corresponding to the context groups.
 18. The system of claim 17,wherein the instructions which, when executed by the one or moreprocessors, further cause the system to perform a training operation toprovide the set of timing tables based on the group number and anotherlayout context including the cell.
 19. The system of claim 16, whereinthe timing analysis is performed subsequent to a synthesis operation anda placement and routing operation.
 20. A non-transitory computerreadable storage medium, comprising instructions which, when executed bya processor, perform the steps of: accessing a layout of an integratedcircuit (IC), the layout comprising a cell; recognizing a representativecontext group for the cell from a set of context groups based on alayout context of the cell in the layout, the context group beingassociated with a representative timing table different from timingtables of remaining context groups in the set of context groups; andperforming a timing analysis on the layout to determine whether thelayout complies with a timing constraint rule according to therepresentative timing table.